1. Field of the Invention
This invention relates to high-density lead frames, packaging technology containing such lead frames and methods of attaching a silicon die onto a lead frame. More particularly, the present invention relates to high-reliability lead frames and packaging methods that provide excellent resistance to moisture and moisture-related problems, such as delamination and warping.
2. Description of the Related Art
Semiconductor integrated circuits are usually mounted on lead frames, each circuit thereafter being encapsulated in a plastic package formed by an injection molding process. FIG. 1 shows an example of a first generation copper lead frame 100. The lead frame 100 includes a plurality of solid copper die-attach platforms 110. Each die-attach platform 110 is adapted to support a single semiconductor die (not shown). The die attach platforms 110 of the lead frame 100 have about the same dimensions as the semiconductor die they are designed to support. On either side of each die-attach platform 110 are leads 115. Each die-attach platform 110 is attached to one of the two lead frame side rails 105 as well as to the lead frame center rail 135. To attach the semiconductor dies onto the solid copper die-attach platforms 110, an adhesive (such as silver epoxy paste) is applied to each die-attach platform 110, and the semiconductor die is adhered thereon. A wire bonding process is then typically carried out to attach fine gold wires between the semiconductor die and the leads 115. The assembly is then enclosed in a mold and molding compound is injected therein to encapsulate the silicon die into the packages. The molding compound is injected at high temperature, most often at or around 175-185 degrees C, and thereafter cooled to room temperature. The resulting packages are then trimmed from the lead frames 100, the leads 112 appropriately bent and shaped, and the packages separated from one another in a singulation process.
The heating of the lead frame assembly to a temperature suitable for plastic injection molding and subsequent cooling to room temperature, however, causes problems that have been traced to the mismatch in the Coefficient of Thermal Expansion (hereafter "CTE") of the constituent materials of the semiconductor package. Indeed, the CTE of the silicon die is about 2.2 Parts Per Million per degree C (hereafter "PPM"/degree C), while the CTE of the plastic molding compound is about 8-12 PPM/degree C and that of the copper lead frame 100 is about 17 PPM/degree C. Due at least in part to these rather larger CTE mismatches, packages manufactured utilizing this or similar lead frame technologies tend to warp as the constituent materials thereof expand and shrink to differing extents and rates.
FIG. 6 depicts a side view of a semiconductor package 600 and the leads 115 protruding therefrom. After the high temperature plastic injection molding and subsequent cooling processes, the mismatch in the CTE between the semiconductor die, the plastic molding compound and the copper lead frame 100 causes the package 600 to warp as it cools to room temperature. The extent of this warpage is illustrated in FIG. 6 by the dimensional arrow labeled W, which represents a measure of the deformation undergone by the package 600 during the heating and/or cooling processes or during a subsequent high temperature process, such as a solder reflow process. The lead frame architecture shown in FIG. 1, for example, typically leads to a warpage measure W of about 4-5 mils for a Thin Outline Small Semiconductor Package (hereafter "TSOP") having a thickness of about 40 mils, or about 1 millimeter.
In an effort to mitigate the warping effects of the solid copper die attach platforms 110 shown in FIG. 1, the semiconductor industry turned to the lead frames having an architecture similar to that shown at 200 in FIG. 2. As shown in FIG. 2, the lead frame 200 includes die attach platforms 210 comprising platform cutouts 220 defining an "XX"-like shape, lead frame side rails 205 and a lead frame center rail 235. The cutouts 220 reduce the amount of copper platform material supporting the semiconductor die (not shown) and thus somewhat reduce the warpage W experienced by the resulting semiconductor package as it undergoes the plastic injection molding and cooling processes and/or other thermal cycling processes. As shown in FIG. 2, each die attach platform 210 is connected to one of the side rails 205 as well as to the center rail 235. Although an improvement over the lead frame architecture of FIG. 1, the lead frame of FIG. 2 still results in an unacceptable degree of warpage W, due to the large area interfaces and CTE mismatches between the copper lead frame 200, the molding compound and the silicon die.
In a further effort to control this warping phenomenon and the delamination and package cracking (internal and/or external) problems associated therewith, lead frame designers were drawn to design alternative lead frame configurations and die attach platforms, such as shown in FIG. 3. FIG. 3 shows a lead frame 300, including side rails 305, a center rail 335, leads 315 and die attach platforms 310 comprising platform interior supports 330 attached to platform frames 325. The platform frames 325 have about the same footprint as the die attach platforms 110 of FIG. 1, but with the interior portion thereof cut out to define the platform interior supports 330. The platform interior supports 330, as shown in FIG. 3, include a meshwork of paddles interconnected by thin wire-like runners. Each semiconductor die (not shown) is supported, therefore, by a platform frame 325 and by the platform interior supports 330 associated with the platform frame 325. These die attach platforms 310, although an improvement over the designs shown in FIGS. 1 and 2, nevertheless exhibit a significant degree of warpage W as a result of thermal cycling and the ingress and egress of moisture into and out of the resulting package. Indeed, the surface area of the die attach platforms 310 is still about 69% of the total surface area of the semiconductor die to be attached thereon. Therefore, a significant area of contact remains between the thermally mismatched copper die attach platform 310 and the silicon die, as well as between the copper die attach platform and the molding compound. Typically, the die attach platforms 310 of FIG. 3 leads to a warpage W of about 2-3 mils for a TSOP package having a thickness of about 40 mils and to significant delamination problems as the constituent materials of the resultant package expand and contract to differing degrees as the device cools.
Still further efforts to reduce the warpage W have led to the lead frame architecture shown in FIG. 4. As shown therein, the lead frame 400 includes lead frame side rails 405, a center rail 435, leads 415 and die attach platforms 410. Each die attach platform 410 has a generally "II"-like shape, configured as a pair of facing and spaced-apart platform runners (perpendicular to the side rails 405 and to the center rail 435) to support the silicon die (not shown). The facing and spaced apart runners of the die attach platform 410 define an empty space 420 therebetween. Whereas two of the sides of the silicon die are supported by the facing and spaced apart runners of the die attach platform 410, the middle portion of the die is suspended over the space 420. As with the die attach platforms of the lead frames of FIGS. 1, 2 and 3, the die attach platform 410 of FIG. 4 is attached to one of the side rails 405 as well as to the center rail 435. Despite a lower contact area between the copper die attach platform 410 and the silicon die and a lower contact area between the die attach platform 410 and the molding compound, the lead frame architecture of FIG. 4 still results in a warpage factor W of abut 2-4 mils for a 40 mils thick TSOP package, with the accompanying defects and delamination problems occasioned by such warpage.
Standard J-STD-020, "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface-Mount Devices", promulgated by JEDEC (Joint Electron Device Engineering Council), the semiconductor engineering standardization body of the Electronic Industries Alliance (EIA), is a widely accepted standard for measuring the moisture sensitivity of semiconductor packages made with moisture-permeable materials. Standard J-STD-020 (incorporated herein by reference in its entirety), and revisions thereof may be found at the JEDEC World Wide Web site, at URL http:.backslash..backslash.www.jedec.org. This standard defines moisture levels that measure the reliability of the package relative to moisture. Currently, six MSL levels are defined, from Moisture Sensitive Level (hereafter "MSL")1 to MSL 6, with lower MSL numbers indicating high reliability and low moisture sensitivity and higher numbers indicating low reliability and high moisture sensitivity.
Semiconductor packages manufactured with the lead frame 100 of FIG. 1, after testing as per JEDEC standard J-STD-020, are typically assigned an MSL of 5, because of relatively high sensitivity to moisture, leading to possible subsequent delamination of the plastic from the die and/or from the lead frame, as well as internal or external package cracks (in extreme cases) as the moisture within the package attempts to outgas therefrom during solder reflow, for example. Similarly, the lead frame architectures of FIGS. 2, 3 and 4 are typically assigned an MSL of between 3 and 5, indicating a relatively high sensitivity to moisture, and pointing to the likelihood of significant moisture and thermal cycling-related problems, such as delamination, die lifting, internal cracks and like defect-inducing phenomena.
What is needed, therefore, are novel high reliability lead frames, packaging technologies and methods of attaching dies onto such novel high reliability lead frames that are less sensitive to moisture and to the problems associated with packages having high moisture sensitivities. Also needed are lead frames that reduce the warpage W of semiconductor devices as they undergo processes having a high thermal gradient such as, for example, reflow processes.